The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Referring now to FIG. 1, a functional block diagram of an exemplary system on chip (SoC) 202 is shown. For example only, the SoC 202 may be used for a third generation (3G) mobile communications device or any other computing device. The SoC 202 includes a processor 204 that executes software. For example, the processor 204 may execute the operating system for the SoC 202, the user interface for the SoC 202, and user programs, such as a web browser.
The processor 204 may execute code out of a read-only memory (ROM) 206, nonvolatile storage 208, and/or memory 210. The ROM 206 may be used to store the operating system and user interface. Nonvolatile storage 208 may be used to store user programs, such as a web browser. Memory 210 may be used to cache data from nonvolatile storage 208.
Memory 210 and nonvolatile storage 208 may be external to the SoC 202 and may communicate with the processor 204 via a bridge controller 212. Data from the bridge controller 212 may be cached in a level 1 (L1) static random access memory (SRAM) cache 220 and a level 2 (L2) SRAM cache 222. The processor 204 may communicate with a general digital signal processor (DSP) 224. In various implementations, the general DSP 224 may perform tasks such as audio and video compression and decompression. The general DSP may store data upon which the general DSP 224 is operated in a DSP SRAM 226.
The processor 204 may communicate with a video accelerator 230 that performs graphic operations used for displaying graphics, text, and video. The video accelerator 230 may store data, such as video frames, in a scratch pad SRAM 232. The processor 204 may establish network communication, whether wired or wireless. The processor 204 may communicate with a protocol stack processor 240, which handles layers of the protocol stack, such as the network layer and transport layer.
The protocol stack processor 240 may store packets and state variables in on-chip SRAM, such as a scratch pad SRAM 242, or in nonvolatile storage 244, which may be external to the SoC 202. Data from nonvolatile storage 244 may be cached in an L1 SRAM 246. The protocol stack processor 240 may pass raw data to a baseband DSP 250. The baseband DSP 250 may store temporary data in a DSP SRAM 252. The baseband DSP 250 may provide binary data to an RF module 254 for transmission via an antenna 256. Similarly, the RF module 254 may transmit data from the antenna 256 to the baseband DSP 250.
As can be appreciated, the layout of blocks of SRAM with respect to memory-using components of the SoC are determined in advance and cannot be readily changed after manufacturing. The performance demands on the blocks of SRAM may change during the life of the SoC. In addition, different purchasers of first and second SoCs having the same common components may have different performance objectives that require different amounts of SRAM. Therefore, different SoCs need to be designed and manufactured, which is costly.